The present invention generally relates to a method and circuit for controlling the output voltage of a DC--DC converter, and, more particularly, to a method and circuit for controlling the output voltage of a DC--DC converter used to supply operating power to various semiconductor integrated circuit devices (ICs), such as central processing units (CPU) and memory devices (RAM and ROM).
FIG. 1 is a schematic circuit diagram of a conventional DC--DC converter 1. The DC--DC converter 1 includes a plurality of stand-alone elements and a control circuit 2 formed on a single chip semiconductor integrated circuit device. An output transistor 3, which is preferably an enhancement type N-channel MOS transistor, has a gate for receiving an output signal SG1 of the control circuit 2, a drain for receiving a DC power supply voltage Vin, and a source connected to an output terminal 5 via an output coil 4. The output terminal 5 is connected to a semiconductor integrated circuit device (not illustrated) as a load, and an output voltage Vout is output from therefrom. The output terminal 5 is connected to ground GND via a smoothing capacitor 7. The smoothing capacitor 7 and the output coil 4 form a smoothing circuit for smoothing the output voltage Vout. The output terminal 5 is further connected to the input terminal of the control circuit 2 via a resistor 8. A flywheel diode 6, which is preferably a Schottky diode, has a cathode connected to the source of the output transistor 3 and an anode connected to the ground GND.
The control circuit 2 includes an error amplification circuit 11, a PWM (pulse width modulation) comparator 12, a triangular wave oscillation circuit 13, and an output circuit 14. The error amplification circuit 11 compares the output voltage Vout, supplied to its inverting input terminal, and a reference voltage Vref supplied to its non-inverting input terminal, amplifies the voltage difference of these voltages, and supplies an error output signal SG2 to the PWM comparator 12. A series circuit of a phase compensation capacitor 15 and a resistor 16 is connected between the output terminal the error amplification circuit 11 and its inverting input terminal. The series circuit prevents oscillation of the error output signal SG2.
The PWM comparator 12 compares the error output signal SG2, supplied to its non-inverting input terminal, and a triangular wave signal SG3 from the triangular wave oscillation circuit 13, supplied to the inverting input terminal, and supplies a duty control signal SG4 to the output circuit 14. The duty control signal SG4 is a pulse signal having an L level when the level of the triangular wave signal SG3 exceeds the level of the error output signal SG2 and having an H level when the level of the triangular wave signal SG3 is below the level of the error output signal SG2. The output circuit 14 receives the duty control signal SG4 from the PWM comparator 12 and supplies a duty control output signal SG1 to the gate of the output transistor 3. The output transistor 3 is turned on or off in accordance with the duty control output signal SG1, and the output voltage Vout having a predetermined voltage (reference voltage Vref) is output from the output terminal 5.
Specifically, when the current consumption of a load connected to the output terminal 5 increases, the output voltage Vout drops. Hereupon, the voltage difference between the output voltage Vout and the reference voltage Vref increases, and the level of the error output signal SG2 rises. Because of the rise of the error output signal SG2, the H level period of the duty control signal SG4 is prolonged (duty ratio increases). In other words, the period when the level of the triangular wave signal SG3 exceeds the level of the error output signal SG2 is shortened and the period when the level of the triangular signal SG3 goes below the level of the error output signal SG2 is prolonged. When the duty ratio increases, the output signal SG1 having a high duty ratio is supplied to the output transistor 3. As a result, the on time of the output transistor 3 is prolonged, and the voltage value of the output voltage Vout increases due to the DC power supply voltage Vin.
When the voltage difference between the output voltage Vout and the reference voltage Vref decreases in accordance with the rise of the output voltage Vout, the rising of the error output signal SG2 becomes slow. Hereupon, the H level period of the duty control signal SG4 is shortened (duty ratio decreases). In other words, the period when the level of the triangular wave signal SG3 exceeds the level of the error output signal SG2 is prolonged and the period when the level of the triangular wave signal SG3 goes below the level of the error output signal SG2 is shortened. When the duty ratio is reduced, the output signal SG1 having a low duty ratio is supplied to the output transistor 3. As a result, the on time of the output transistor 3 is shortened, and the rise of the voltage value of the output voltage Vout becomes slow. By repeating this operation, the output voltage Vout converges on the reference voltage Vref, and a stable output voltage Vout is obtained.
A certain amount of time is necessary until the output voltage Vout converges on the predetermined voltage (reference voltage Vref) after the fluctuation of output voltage Vout. Most of this time is occupied by the delay time generated by the phase compensation capacitor 15 connected between the input/output terminals of the error amplification circuit 11. Therefore, as shown in FIG. 2, the DC--DC converter 1 cannot respond quickly to a sudden increase of the current consumption of the load and the output voltage Vout has a large drop. The drop of the output voltage Vout affects the operation of the load (i.e., semiconductor integrated circuit device) connected to the output terminal 5.
It is an object of the present invention to provide a method and circuit for controlling a DC--DC converter to output a stable output voltage.